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» Power distribution techniques for dual VDD circuits
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CODES
2005
IEEE
15 years 3 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...
90
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IPPS
2007
IEEE
15 years 3 months ago
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
1 FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-e...
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas A...
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
14 years 11 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 2 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
SLIP
2003
ACM
15 years 2 months ago
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement
In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framew...
Navaratnasothie Selvakkumaran, Phiroze N. Parakh, ...