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» Power minimization for dynamic PLAs
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EUROPAR
2009
Springer
15 years 1 months ago
Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations
Abstract. We present a hardware mechanism which dynamically detects uniform and affine vectors used in Graphics Processing Units, to minimize pressure on the register file and redu...
Sylvain Collange, David Defour, Yao Zhang
78
Voted
ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
15 years 2 months ago
Inductive interconnect width optimization for low power
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
Magdy A. El-Moursy, Eby G. Friedman
VLSID
2004
IEEE
146views VLSI» more  VLSID 2004»
15 years 10 months ago
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ISCAS
1999
IEEE
300views Hardware» more  ISCAS 1999»
15 years 1 months ago
Ripple correlation control, with some applications
Ripple correlation control is a nonlinear control approach applicable to power electronic circuits. It makes use of voltage, current, or power ripple and correlates this with swit...
P. T. Krein
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
15 years 3 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu