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» Power minimization for dynamic PLAs
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RTAS
2008
IEEE
15 years 4 months ago
Real-Time Dynamic Power Management through Device Forbidden Regions
Dynamic Power Management (DPM) techniques are crucial in minimizing the overall energy consumption in real-time embedded systems. The timing constraints of real-time applications ...
Vinay Devadas, Hakan Aydin
HICSS
2007
IEEE
125views Biometrics» more  HICSS 2007»
15 years 4 months ago
Stochastic Model for Power Grid Dynamics
We introduce a stochastic model that describes the quasistatic dynamics of an electric transmission network under perturbations introduced by random load fluctuations, random rem...
Marian Anghel, Kenneth A. Werley, Adilson E. Motte...
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
15 years 2 months ago
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
88
Voted
ASPDAC
2006
ACM
110views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Switching-activity driven gate sizing and Vth assignment for low power design
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
ACCV
1998
Springer
15 years 1 months ago
VR Models from Epipolar Images: An Approach to Minimize Errors in Synthesized Images
A new paradigm, the minimization of errors in synthesized images, is introduced to organically combine Computer Vision and Computer Graphics for Virtual Reality applications. Based...
Mikio Shinya, Takafumi Saito, Takeaki Mori, Noriyo...