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» Power minimization for dynamic PLAs
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DATE
2009
IEEE
111views Hardware» more  DATE 2009»
15 years 4 months ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb...
ISCAS
1995
IEEE
107views Hardware» more  ISCAS 1995»
15 years 1 months ago
Power Dissipation in Deep Submicron CMOS Digital Circuits
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
R. X. Gu, Mohamed I. Elmasry
62
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ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
15 years 6 months ago
Evaluating Techniques for Exploiting Instruction Slack
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
Yau Chin, John Sheu, David Brooks
ICIP
2004
IEEE
15 years 11 months ago
Joint object-based video encoding and power management for energy efficient wireless video communications
In this paper, we consider dynamic resource allocation for object-based wireless video communications. In object-based video coding, a video frame is comprised of objects that are...
Haohong Wang, Yiftach Eisenberg, Fan Zhai, Aggelos...
TPDS
2008
199views more  TPDS 2008»
14 years 9 months ago
DCMP: A Distributed Cycle Minimization Protocol for Peer-to-Peer Networks
Abstract-- Broadcast-based Peer-to-Peer (P2P) networks, including flat (e.g., Gnutella) and two-layer super-peer implementations (e.g., Kazaa), are extremely popular nowadays due t...
Zhenzhou Zhu, Panos Kalnis, Spiridon Bakiras