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» Power optimization and management in embedded systems
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ICCAD
2000
IEEE
95views Hardware» more  ICCAD 2000»
15 years 3 months ago
Test of Future System-on-Chips
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
Yervant Zorian, Sujit Dey, Mike Rodgers
CDC
2008
IEEE
204views Control Systems» more  CDC 2008»
15 years 5 months ago
Dynamic ping optimization for surveillance in multistatic sonar buoy networks with energy constraints
— In this paper we study the problem of dynamic optimization of ping schedule in an active sonar buoy network deployed to provide persistent surveillance of a littoral area throu...
Anshu Saksena, I-Jeng Wang
ESTIMEDIA
2009
Springer
14 years 8 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...
SCOPES
2004
Springer
15 years 4 months ago
Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization
For mobile embedded systems, the energy consumption is a limiting factor because of today’s battery capacities. Besides the processor, memory accesses consume a high amount of en...
Heiko Falk, Manish Verma
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CODES
2004
IEEE
15 years 2 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan