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DAC
1996
ACM
13 years 10 months ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
ICC
2007
IEEE
118views Communications» more  ICC 2007»
14 years 17 days ago
Peak Tracking Algorithm for Galileo-Based Positioning in Multipath Fading Channels
ACT Line-of-Sight (LOS) delay estimation with high accuracy is a pre-requisite for reliable location via satellite systems. The future European satellite positioning system, Galile...
Mohammad Zahidul H. Bhuiyan, Elena Simona Lohan, M...
DFT
2005
IEEE
132views VLSI» more  DFT 2005»
13 years 8 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
14 years 21 days ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
13 years 11 months ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...