390 search results - page 23 / 78 » Power system on a chip (PSoC) |
NIPS
1996
15 years 1 months ago
1996
We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decod...
104
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ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
ISVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
119
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ASPLOS
2004
ACM
15 years 5 months ago
2004
ACM
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...