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ISCAS
2005
IEEE
140views Hardware» more  ISCAS 2005»
15 years 7 months ago
A 16-bit low-power microcontroller with monolithic MEMS-LC clocking
Abstract—Low-power, single-chip integrated systems are prevailing in remote applications due to the increasing power and delay cost of inter-chip communication compared to on-chi...
Robert M. Senger, Eric D. Marsman, Michael S. McCo...
ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
15 years 7 months ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
ISCAS
2008
IEEE
138views Hardware» more  ISCAS 2008»
15 years 8 months ago
High-speed adaptive RF phased array
— We demonstrate dynamic power maximization and synchronization of a wireless RF communication link through adaptation of the radiation pattern of a phased array at the transmitt...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
ICMCS
2006
IEEE
154views Multimedia» more  ICMCS 2006»
15 years 8 months ago
Design of Audio and Video decoder for the T-DMB Receiver
We present a low-power architectural MPEG-4 part-10 AVC/H.264 video and MPEG-4 BSAC audio decoder chip capable of delivering high-quality and high-compression in wireless multimed...
Bontae Koo, Juhyun Lee, Sekho Lee, Jinkyu Kim, Min...
ISCA
2012
IEEE
281views Hardware» more  ISCA 2012»
13 years 4 months ago
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...