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COMBINATORICS
2004
93views more  COMBINATORICS 2004»
14 years 11 months ago
Degree Powers in Graphs with Forbidden Subgraphs
For every real p > 0 and simple graph G, set f (p, G) = uV (G) dp (u) , and let (r, p, n) be the maximum of f (p, G) taken over all Kr+1-free graphs G of order n. We prove tha...
Béla Bollobás, Vladimir Nikiforov
AAAI
2011
13 years 11 months ago
Pushing the Power of Stochastic Greedy Ordering Schemes for Inference in Graphical Models
We study iterative randomized greedy algorithms for generating (elimination) orderings with small induced width and state space size - two parameters known to bound the complexity...
Kalev Kask, Andrew Gelfand, Lars Otten, Rina Decht...
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
15 years 5 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 2 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
DAC
2002
ACM
15 years 12 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...