For every real p > 0 and simple graph G, set f (p, G) = uV (G) dp (u) , and let (r, p, n) be the maximum of f (p, G) taken over all Kr+1-free graphs G of order n. We prove tha...
We study iterative randomized greedy algorithms for generating (elimination) orderings with small induced width and state space size - two parameters known to bound the complexity...
Kalev Kask, Andrew Gelfand, Lars Otten, Rina Decht...
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...