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» Pragmatic integrated scheduling for clustered VLIW architect...
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IPPS
1998
IEEE
13 years 10 months ago
Partitioned Schedules for Clustered VLIW Architectures
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
Marcio Merino Fernandes, Josep Llosa, Nigel P. Top...
MICRO
2000
IEEE
67views Hardware» more  MICRO 2000»
13 years 10 months ago
Modulo scheduling for a fully-distributed clustered VLIW architecture
F. Jesús Sánchez, Antonio Gonz&aacut...
DAC
2002
ACM
14 years 7 months ago
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
Andrea Bona, Mariagiovanna Sami, Donatella Sciuto,...
FPGA
2009
ACM
209views FPGA» more  FPGA 2009»
14 years 1 months ago
SPR: an architecture-adaptive CGRA mapping tool
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
Stephen Friedman, Allan Carroll, Brian Van Essen, ...
CASES
2001
ACM
13 years 10 months ago
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, ...