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GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
15 years 11 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
CORR
2010
Springer
99views Education» more  CORR 2010»
15 years 5 months ago
Locating phase transitions in computationally hard problems
We discuss how phase-transitions may be detected in computationally hard problems in the context of anytime algorithms. Treating the computational time, value and utility functions...
B. Ashok, T. K. Patra
CSREAESA
2004
15 years 6 months ago
A High Performance, Low Area Overhead Carry Lookahead Adder
Adders are some of the most critical data path circuits requiring considerable design effort in order to "squeeze" out as much performance gain as possible. Many adder d...
James Levy, Jabulani Nyathi
BMCBI
2007
148views more  BMCBI 2007»
15 years 5 months ago
p53FamTaG: a database resource of human p53, p63 and p73 direct target genes combining in silico prediction and microarray data
Background: The p53 gene family consists of the three genes p53, p63 and p73, which have polyhedral non-overlapping functions in pivotal cellular processes such as DNA synthesis a...
Elisabetta Sbisà, Domenico Catalano, Giorgi...
CAL
2006
15 years 5 months ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck