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» Predicting defects with program dependencies
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RTSS
1994
IEEE
15 years 3 months ago
Bounding Worst-Case Instruction Cache Performance
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
ISCAPDCS
2003
15 years 1 months ago
Dynamic Simultaneous Multithreaded Architecture
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
Daniel Ortiz Arroyo, Ben Lee
HICSS
1999
IEEE
72views Biometrics» more  HICSS 1999»
15 years 4 months ago
Software Reliability as a Function of User Execution Patterns
Assessing the reliability of a software system has always been an elusive target. A program may work very well for a number of years and this same program may suddenly become quit...
John C. Munson, Sebastian G. Elbaum
99
Voted
MICRO
2003
IEEE
142views Hardware» more  MICRO 2003»
15 years 5 months ago
Hardware Support for Control Transfers in Code Caches
Many dynamic optimization and/or binary translation systems hold optimized/translated superblocks in a code cache. Conventional code caching systems suffer from overheads when con...
Ho-Seop Kim, James E. Smith
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 4 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi