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RTAS
2008
IEEE
15 years 4 months ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley
ICPPW
2002
IEEE
15 years 2 months ago
High Performance Air Pollution Simulation Using OpenMP
The aim of this work is to provide a high performance air quality simulation using the STEM-II (Sulphur Transport Eulerian Model 2) program. First of all we optimize the sequentia...
Marta Parada, María J. Martín, Ramon...
HICSS
1996
IEEE
102views Biometrics» more  HICSS 1996»
15 years 1 months ago
Evaluation of Parallel Logic Simulation Using DVSIM
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulati...
Gerd Meister
ICS
2000
Tsinghua U.
15 years 1 months ago
Using complete system simulation to characterize SPECjvm98 benchmarks
Complete system simulation to understand the influence of architecture and operating systems on application execution has been identified to be crucial for systems design. While t...
Tao Li, Lizy Kurian John, Narayanan Vijaykrishnan,...
71
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DDECS
2006
IEEE
140views Hardware» more  DDECS 2006»
15 years 1 months ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Zbysek Gajda