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    SLIP
    2004
    ACM
    86views Computer Networks» more  SLIP 2004»
    Prediction of interconnect net-degree distribution based on Rent's rule
    15 years 2 months ago
    Prediction of interconnect net-degree distribution based on Rent's rule
    Download  www.sliponline.org
    Tao Wan, Malgorzata Chrzanowska-Jeske
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    SLIP
    2000
    ACM
    64views Computer Networks» more  SLIP 2000»
    Prediction of interconnect fan-out distribution using Rent's rule
    15 years 1 months ago
    Prediction of interconnect fan-out distribution using Rent's rule
    Download  www.ece.gatech.edu
    Based on Rent’s rule, a well-established empirical relationship, a rigorous derivation of the interconnect fan-out distribution for random logic networks is performed. Through c...
    Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, ...
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    SLIP
    2003
    ACM
    111views Computer Networks» more  SLIP 2003»
    Fast estimation of the partitioning rent characteristic using a recursive partitioning model
    15 years 2 months ago
    Fast estimation of the partitioning rent characteristic using a recursive partitioning model
    Download  escher.elis.ugent.be
    In the past, a priori interconnect prediction, based on Rent’s rule, has been applied mainly for technology evaluation and roadmap applications. These applications do not requir...
    Joni Dambre, Dirk Stroobandt, Jan Van Campenhout
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    GLVLSI
    2008
    IEEE
    197views VLSI» more  GLVLSI 2008»
    Efficient tree topology for FPGA interconnect network
    14 years 9 months ago
    Efficient tree topology for FPGA interconnect network
    Download  www-asim.lip6.fr
    This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
    Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
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    99
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    SLIP
    2009
    ACM
    226views Computer Networks» more  SLIP 2009»
    Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
    15 years 4 months ago
    Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
    Download  www.sliponline.org
    Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
    Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
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