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ICIP
2005
IEEE
16 years 6 months ago
High throughput 2D DCT/IDCT processor for video coding
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron
ANOR
2008
96views more  ANOR 2008»
15 years 5 months ago
How good are SPT schedules for fair optimality criteria
Abstract We consider the following scheduling setting: a set of
Eric Angel, Evripidis Bampis, Fanny Pascual
GLOBECOM
2010
IEEE
15 years 3 months ago
Cooperative Relay Scheduling under Partial State Information in Energy Harvesting Sensor Networks
Abstract--Sensors equipped with energy harvesting and cooperative communication capabilities are a viable solution to the power limitations of Wireless Sensor Networks (WSNs) assoc...
Huijiang Li, Neeraj Jaggi, Biplab Sikdar
WSC
2008
15 years 7 months ago
A review of scheduling theory and methods for semiconductor manufacturing cluster tools
Cluster tools, which combine several single-wafer processing modules with wafer handling robots in a closed environment, have been increasingly used for most wafer fabrication pro...
Tae-Eog Lee
EDBT
2009
ACM
218views Database» more  EDBT 2009»
15 years 11 months ago
Data integration flows for business intelligence
Business Intelligence (BI) refers to technologies, tools, and practices for collecting, integrating, analyzing, and presenting large volumes of information to enable better decisi...
Umeshwar Dayal, Malú Castellanos, Alkis Sim...