2544 search results - page 171 / 509 » Process pipeline scheduling |
142
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ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
145
Voted
PG
2003
IEEE
15 years 11 months ago
2003
IEEE
Interactive visualization of complex, real-world light sources has so far not been feasible. In this paper, we present an hardware accelerated direct lighting algorithm based on a...
163
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DAC
1999
ACM
15 years 10 months ago
1999
ACM
This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution mode...
158
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CAIP
1997
Springer
15 years 10 months ago
1997
Springer
: A new hardware structure for implementation of soft morphological filters is presented in this paper. This is based on the modification of the majority gate technique. A pipeline...
213
Voted
IFIPPACT
1994
15 years 7 months ago
1994
: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope ...