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IJAR
1998
76views more  IJAR 1998»
14 years 9 months ago
Multi-site scheduling with fuzzy concepts
The objective of multi-site scheduling is to support the scheduling activities of a global scheduler and schedulers in distributed production plants in a cooperative way. A global...
Jürgen Sauer, Gerd Suelmann, Hans-Jürgen...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
15 years 3 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
DELTA
2010
IEEE
15 years 2 months ago
Notations for Multiphase Pipelines
— FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture ...
Christopher T. Johnston, Donald G. Bailey, Paul J....
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
15 years 2 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
FPGA
2009
ACM
209views FPGA» more  FPGA 2009»
15 years 4 months ago
SPR: an architecture-adaptive CGRA mapping tool
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
Stephen Friedman, Allan Carroll, Brian Van Essen, ...