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» Processing-in-Memory: Exploring the Design Space
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106
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DAC
2005
ACM
15 years 2 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
15 years 2 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
COORDINATION
2008
Springer
15 years 2 months ago
Actors with Multi-headed Message Receive Patterns
Abstract. The actor model provides high-level concurrency abstractions to coordinate simultaneous computations by message passing. Languages implementing the actor model such as Er...
Martin Sulzmann, Edmund S. L. Lam, Peter Van Weert
AAAI
2004
15 years 2 months ago
Methods for Boosting Revenue in Combinatorial Auctions
We study the recognized open problem of designing revenuemaximizing combinatorial auctions. It is unsolved even for two bidders and two items for sale. Rather than pursuing the pu...
Anton Likhodedov, Tuomas Sandholm
93
Voted
JRTIP
2008
249views more  JRTIP 2008»
15 years 18 days ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...