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DAC
1996
ACM
15 years 1 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
TVCG
2011
257views more  TVCG 2011»
14 years 4 months ago
A Spatially Augmented Reality Sketching Interface for Architectural Daylighting Design
—We present an application of interactive global illumination and spatially augmented reality to architectural daylight modeling that allows designers to explore alternative desi...
Yu Sheng, Theodore C. Yapo, Christopher Young, Bar...
ECWEB
2005
Springer
149views ECommerce» more  ECWEB 2005»
15 years 3 months ago
Architecture of a Semantic XPath Processor. Application to Digital Rights Management
This work describes a novel strategy for designing an XPath processor that acts over an RDF mapping of XML. We use a modelmapping approach to represent instances of XML and XML Sch...
Rubén Tous, Roberto García, Eva Rodr...
SLIP
2003
ACM
15 years 3 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 3 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...