Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
—We present an application of interactive global illumination and spatially augmented reality to architectural daylight modeling that allows designers to explore alternative desi...
Yu Sheng, Theodore C. Yapo, Christopher Young, Bar...
This work describes a novel strategy for designing an XPath processor that acts over an RDF mapping of XML. We use a modelmapping approach to represent instances of XML and XML Sch...
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...