2700 search results - page 281 / 540 » Processor Architectures for Ontogenesis |
144
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
Time skewing is a compile-time optimization that can provide arbitrarily high cache hit rates for a class of iterative calculations, given a sufficient number of time steps and s...
159
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DATE
1998
IEEE
15 years 10 months ago
1998
IEEE
The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than today's processing archi...
157
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
The emerging three-dimensional integrated circuit (3D IC) is beneficial for various applications from both area and performance perspectives. While the general trend in processor...
131
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DATE
1998
IEEE
15 years 10 months ago
1998
IEEE
We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of severa...
157
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AMAST
2008
Springer
15 years 8 months ago
2008
Springer
This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of in...