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» Processor Architectures for Ontogenesis
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HPCA
2003
IEEE
16 years 4 months ago
Caches and Hash Trees for Efficient Memory Integrity
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, M...
CADE
2007
Springer
16 years 4 months ago
Formal Device and Programming Model for a Serial Interface
Abstract. The verification of device drivers is essential for the pervasive verification of an operating system. To show the correctness of device drivers, devices have to be forma...
Eyad Alkassar, Mark A. Hillebrand, Steffen Knapp, ...
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
16 years 1 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...
ICCAD
2003
IEEE
188views Hardware» more  ICCAD 2003»
16 years 1 months ago
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization
Abstract: In this paper, we present an interprocessor communication-aware task scheduling algorithm applicable to a multiprocessor system executing an application with dependent ta...
Girish Varatkar, Radu Marculescu
MSWIM
2009
ACM
15 years 11 months ago
On power and energy trends of IEEE 802.11n PHY
The main contribution of this work is to decipher the power and energy characteristics of IEEE 802.11 PHY. In this work, we implement an IEEE 802.11n receiver and transmitter benc...
Balaji V. Iyer, Thomas M. Conte