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» Processor Architectures for Ontogenesis
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ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
15 years 3 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ISCAS
2005
IEEE
128views Hardware» more  ISCAS 2005»
15 years 3 months ago
Development of an audio player as system-on-a-chip using an open source platform
— Open source software are becoming more widely-used, notably in the server and desktop applications. For embedded systems development, usage of open source software can also red...
Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rai...
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MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 3 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
RTAS
2005
IEEE
15 years 3 months ago
Feedback-Based Dynamic Voltage and Frequency Scaling for Memory-Bound Real-Time Applications
Dynamic voltage and frequency scaling is increasingly being used to reduce the energy requirements of embedded and real-time applications by exploiting idle CPU resources, while s...
Christian Poellabauer, Leo Singleton, Karsten Schw...
RTAS
2005
IEEE
15 years 3 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller