142 search results - page 11 / 29 » Processor Memory Co-Exploration on Multiple Abstraction Leve... |
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ISCA
2012
IEEE
13 years 1 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
NIPS
2000
15 years 9 days ago
2000
Theories of object recognition often assume that only one representation scheme is used within one visual-processing pathway. Versatility of the visual system comes from having mu...
ICCAD
2003
IEEE
15 years 7 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ICCD
2006
IEEE
15 years 7 months ago
2006
IEEE
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
118
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EUROPAR
2010
Springer
15 years 1 days ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...