253 search results - page 23 / 51 » Processor Models for Retargetable Tools |
IEEEPACT
2007
IEEE
15 years 6 months ago
2007
IEEE
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
RTCSA
1999
IEEE
15 years 4 months ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
107
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CONCUR
2008
Springer
15 years 1 months ago
2008
Springer
Software transactional memory (STM) offers a disciplined concurrent programming model for exploiting the parallelism of modern processor architectures. This paper presents the firs...
124
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DDECS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...