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DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 8 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
SOFTVIS
2010
ACM
15 years 5 months ago
TIE: an interactive visualization of thread interleavings
Multi-core processors have become increasingly prevalent, driving a software shift toward concurrent programs which best utilize these processors. Testing and debugging concurrent...
Gowritharan Maheswara, Jeremy S. Bradbury, Christo...
DAC
2001
ACM
16 years 6 months ago
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
Albert Wang, Earl Killian, Dror E. Maydan, Chris R...
AMAI
2004
Springer
15 years 10 months ago
Using Automatic Case Splits and Efficient CNF Translation to Guide a SAT-solver when Formally Verifying Out-Of-Order Processors
The paper integrates automatically generated case-splitting expressions, and an efficient translation to CNF, in order to formally verify an out-of-order superscalar processor havi...
Miroslav N. Velev
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 10 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...