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ICPP
1996
IEEE
15 years 1 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 1 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
CAL
2006
14 years 9 months ago
A case for fault tolerance and performance enhancement using chip multi-processors
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
Huiyang Zhou
SC
1992
ACM
15 years 1 months ago
Heterogeneous Parallel Programming in Jade
This paper presents Jade, a high-level parallel programming language for managing coarse-grain concurrency. Jade simplifies programming by providing the programmer with the abstra...
Martin C. Rinard, Daniel J. Scales, Monica S. Lam
ESOP
2010
Springer
15 years 7 months ago
Weighted Dynamic Pushdown Networks
We develop a generic framework for the analysis of programs with recursive procedures and dynamic process creation. To this end we combine the approach of weighted pushdown systems...
Alexander Wenner