627 search results - page 96 / 126 » Programming multi-core architectures using Data-Flow techniq... |
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IEEEPACT
2009
IEEE
15 years 9 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
135
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IPPS
2007
IEEE
15 years 8 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
117
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ISCA
1997
IEEE
15 years 6 months ago
1997
IEEE
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
129
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AOSD
2007
ACM
15 years 6 months ago
2007
ACM
Configurability is a major issue in the domain of embedded system software. Existing systems specifically lack good techniques to implement configurability of architectural OS con...
98
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ASPLOS
2008
ACM
15 years 4 months ago
2008
ACM
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...