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IPPS
2007
IEEE
15 years 10 months ago
Experience of Optimizing FFT on Intel Architectures
Automatic library generators, such as ATLAS [11], Spiral [8] and FFTW [2], are promising technologies to generate efficient code for different computer architectures. The library...
Daniel Orozco, Liping Xue, Murat Bolat, Xiaoming L...
ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
15 years 10 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee
ISQED
2007
IEEE
141views Hardware» more  ISQED 2007»
15 years 10 months ago
OPC-Friendly Bus Driven Floorplanning
In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/v...
Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. W...
MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
15 years 10 months ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li
SP
2007
IEEE
148views Security Privacy» more  SP 2007»
15 years 10 months ago
DSSS-Based Flow Marking Technique for Invisible Traceback
Law enforcement agencies need the ability to conduct electronic surveillance to combat crime, terrorism, or other malicious activities exploiting the Internet. However, the prolif...
Wei Yu, Xinwen Fu, Steve Graham, Dong Xuan, Wei Zh...
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