533 search results - page 39 / 107 » Protocol synthesis from timed and structured specifications |
122
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TCAD
2002
15 years 29 days ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
138
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ICCAD
2001
IEEE
15 years 10 months ago
2001
IEEE
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
113
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ENTCS
2010
15 years 1 months ago
2010
Interface automata are a model that allows for the representation of stateful interfaces. In this paper we introduce a variant of interface automata, which we call interface struc...
119
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TC
2008
15 years 1 months ago
2008
RFID (Radio Frequency IDentification) tags need to include security functions, yet at the same time their resources are extremely limited. Moreover, to provide privacy, authenticat...
138
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ICIC
2009
Springer
14 years 11 months ago
2009
Springer
This paper presents an evolutionary method for identifying the gene regulatory network from the observed time series data of gene expression using a system of ordinary differential...