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IPPS
2006
IEEE
15 years 3 months ago
MegaProto/E: power-aware high-performance cluster with commodity technology
In our research project named “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, we have been developing a prototype cluster not based on ASIC or FPGA...
Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, H...
IEEEPACT
2005
IEEE
15 years 3 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
15 years 3 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
ICS
2005
Tsinghua U.
15 years 3 months ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
FPGA
2004
ACM
137views FPGA» more  FPGA 2004»
15 years 3 months ago
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources
As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalab...
Navaratnasothie Selvakkumaran, Abhishek Ranjan, Sa...