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CF
2005
ACM
14 years 11 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
CF
2006
ACM
14 years 11 months ago
Intermediately executed code is the key to find refactorings that improve temporal data locality
The growing speed gap between memory and processor makes an efficient use of the cache ever more important to reach high performance. One of the most important ways to improve cac...
Kristof Beyls, Erik H. D'Hollander
MKWI
2008
126views Business» more  MKWI 2008»
14 years 11 months ago
A Software Architecture for Grid Utilisation in Business Workflows
: Within an enterprise various information systems have to be run. Enterprise Application Integration (EAI) has become a well-established way to integrate such heterogeneous busine...
Stefan Gudenkauf, Wilhelm Hasselbring, Felix Heine...
HPDC
2010
IEEE
14 years 10 months ago
Browsing large scale cheminformatics data with dimension reduction
Visualization of large-scale high dimensional data tool is highly valuable for scientific discovery in many fields. We present PubChemBrowse, a customized visualization tool for c...
Jong Youl Choi, Seung-Hee Bae, Judy Qiu, Geoffrey ...
CCGRID
2010
IEEE
14 years 10 months ago
FaReS: Fair Resource Scheduling for VMM-Bypass InfiniBand Devices
In order to address the high performance I/O needs of HPC and enterprise applications, modern interconnection fabrics, such as InfiniBand and more recently, 10GigE, rely on network...
Adit Ranadive, Ada Gavrilovska, Karsten Schwan