Sciweavers

2555 search results - page 130 / 511
» Quantifiers and Working Memory
Sort
View
ASPLOS
2008
ACM
15 years 5 months ago
Archipelago: trading address space for reliability and security
Memory errors are a notorious source of security vulnerabilities that can lead to service interruptions, information leakage and unauthorized access. Because such errors are also ...
Vitaliy B. Lvin, Gene Novark, Emery D. Berger, Ben...
162
Voted
HPCA
2012
IEEE
13 years 11 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
ICPP
2008
IEEE
15 years 10 months ago
Scalable Dynamic Load Balancing Using UPC
An asynchronous work-stealing implementation of dynamic load balance is implemented using Unified Parallel C (UPC) and evaluated using the Unbalanced Tree Search (UTS) benchmark ...
Stephen Olivier, Jan Prins
143
Voted
JAVA
2001
Springer
15 years 8 months ago
Implementation of a portable software DSM in Java
Rapid commoditization of advanced hardware and progress of networking technology is now making wide area high-performance computing a.k.a. the ‘Grid’ Computing a reality. Sinc...
Yukihiko Sohda, Hidemoto Nakada, Satoshi Matsuoka
138
Voted
EUROPAR
2008
Springer
15 years 5 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler