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134
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ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
16 years 2 months ago
Architectural Support for Run-Time Validation of Control Flow Transfer
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
Yixin Shi, Sean Dempsey, Gyungho Lee
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
16 years 2 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
134
Voted
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
16 years 2 months ago
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm
In this work, we propose a dynamic power-aware issue queue in a general-purpose microprocessor for multimedia applications. Its resources can be adapted at runtime in accordance w...
Yu Bai, R. Iris Bahar
ICCAD
2004
IEEE
260views Hardware» more  ICCAD 2004»
16 years 2 months ago
On interactions between routing and detailed placement
The main goal of this paper is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework...
Devang Jariwala, John Lillis
ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
16 years 2 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...
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