Sciweavers

147 search results - page 10 / 30
» Queue Machines: Hardware Compilation in Hardware
Sort
View
ICFP
2002
ACM
15 years 9 months ago
Compiling scheme to JVM bytecode: : a performance study
We have added a Java virtual machine (henceforth JVM) bytecode generator to the optimizing Scheme-to-C compiler Bigloo. We named this new compiler BiglooJVM. We have used this new...
Bernard P. Serpette, Manuel Serrano
ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
12 years 12 months ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...
ACMMSP
2006
ACM
278views Hardware» more  ACMMSP 2006»
15 years 3 months ago
Atomicity via source-to-source translation
We present an implementation and evaluation of atomicity (also known as software transactions) for a dialect of Java. Our implementation is fundamentally different from prior work...
Benjamin Hindman, Dan Grossman
CDES
2006
184views Hardware» more  CDES 2006»
14 years 10 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
CODES
2006
IEEE
15 years 3 months ago
Retargetable code optimization with SIMD instructions
Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequ...
Manuel Hohenauer, Christoph Schumacher, Rainer Leu...