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DATE
2005
IEEE
93views Hardware» more  DATE 2005»
15 years 5 months ago
Model Reuse through Hardware Design Patterns
Increasing reuse opportunities is a well-known problem for software designers as well as for hardware designers. Nonetheless, current software and hardware engineering practices h...
Fernando Rincón, Francisco Moya, Jesú...
ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
14 years 3 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
FCCM
2006
IEEE
201views VLSI» more  FCCM 2006»
15 years 3 months ago
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers
With advances in reconfigurable hardware, especially field-programmable gate arrays (FPGAs), it has become possible to use reconfigurable hardware to accelerate complex applicatio...
Ronald Scrofano, Maya Gokhale, Frans Trouw, Viktor...
CC
2008
Springer
240views System Software» more  CC 2008»
15 years 1 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
82
Voted
PDPTA
2003
15 years 1 months ago
The Application of Software Process Precedence Relationship Formalisms to Concurrent Hardware Systems
In this paper, precedence constraint combination formalisms defined in the software domain are used to define the behavior of hardware systems. Specifically, AND-join and various ...
Kenneth G. Ricks, David Jeff Jackson, B. Earl Well...