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FPL
2005
Springer
127views Hardware» more  FPL 2005»
15 years 5 months ago
Efficient Hardware Architectures for Modular Multiplication on FPGAs
The computational fundament of most public-key cryptosystems is the modular multiplication. Improving the efficiency of the modular multiplication is directly associated with the...
David Narh Amanor, Viktor Bunimov, Christof Paar, ...
IWSOC
2003
IEEE
137views Hardware» more  IWSOC 2003»
15 years 5 months ago
Hardware Partitioning Software for Dynamically Reconfigurable SoC Design
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibil...
Philippe Brunet, Camel Tanougast, Yves Berviller, ...
CGI
2004
IEEE
15 years 3 months ago
Efficient Hardware for Antialiasing Coverage Mask Generation
An efficient low-cost, low-power hardware implementation of a novel run-time pixel coverage mask generation algorithm for embedded 3-D graphics antialiasing purposes is presented....
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
IFIP12
2007
15 years 1 months ago
Hardware Natural Language Interface
In this paper an efficient architecture for natural language processing is presented, implemented in hardware using FPGAs (Field Programmable Gate Arrays). The system can receive s...
Christos Pavlatos, Alexandros C. Dimopoulos, Georg...
DFT
2006
IEEE
82views VLSI» more  DFT 2006»
15 years 5 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...