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IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
15 years 3 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
IPPS
2006
IEEE
15 years 3 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
ISPD
2006
ACM
126views Hardware» more  ISPD 2006»
15 years 3 months ago
Noise driven in-package decoupling capacitor optimization for power integrity
The existing decoupling capacitance optimization approaches meet constraints on input impedance for package. In this paper, we show that using impedance as constraints leads to la...
Jun Chen, Lei He
AICCSA
2005
IEEE
164views Hardware» more  AICCSA 2005»
15 years 3 months ago
Efficient aggregation of delay-constrained data in wireless sensor networks
Recent years have witnessed a growing interest in the application of wireless sensor networks in unattended environments. Nodes in such applications are equipped with limited ener...
Kemal Akkaya, Mohamed F. Younis, Moustafa Youssef
ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
15 years 3 months ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...