207 search results - page 4 / 42 » RTL Processor Synthesis for Architecture Exploration and Imp... |
DAC
1996
ACM
13 years 10 months ago
1996
ACM
This paper discusses the design of a chip using architectural synthesis. The chip, FADIC, is applied in Digital Audio Broadcasting (DAB) receivers. It shows that architectural syn...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
CHARME
2001
Springer
13 years 10 months ago
2001
Springer
Abstract. We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to d...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...