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CF
2006
ACM
15 years 8 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
15 years 7 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
ATAL
1997
Springer
15 years 7 months ago
A Formal Specification of dMARS
The Procedural Reasoning System (PRS) is the best established agent architecture currently available. It has been deployed in many major industrial applications, ranging from fault...
Mark d'Inverno, David Kinny, Michael Luck, Michael...
SIGGRAPH
2000
ACM
15 years 7 months ago
Accessible animation and customizable graphics via simplicial configuration modeling
Our goal is to embed free-form constraints into a graphical model. With such constraints a graphic can maintain its visual integrity--and break rules tastefully--while being manip...
Tom Ngo, Doug Cutrell, Jenny Dana, Bruce Randall D...
SC
1995
ACM
15 years 7 months ago
Input/Output Characteristics of Scalable Parallel Applications
Rapid increases in computing and communication performance are exacerbating the long-standing problem of performance-limited input/output. Indeed, for many otherwise scalable para...
Phyllis Crandall, Ruth A. Aydt, Andrew A. Chien, D...
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