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FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
15 years 1 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
15 years 10 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
CAMAD
2009
IEEE
15 years 2 months ago
Performance Analysis of Available Bandwidth Estimation Tools for Grid Networks
—Modern large-scale grid computing for processing advanced science and engineering applications relies on geographically distributed clusters. In such highly distributed environm...
Daniel M. Batista, Luciano Chaves, Nelson L. S. da...
IPPS
2003
IEEE
15 years 3 months ago
An Evaluation of Current High-Performance Networks
High-end supercomputers are increasingly built out of commodity components, and lack tight integration between the processor and network. This often results in inefficiencies in ...
Christian Bell, Dan Bonachea, Yannick Cote, Jason ...
DAC
1996
ACM
15 years 2 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen