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» Reducing Power in High-Performance Microprocessors
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DSN
2002
IEEE
15 years 2 months ago
Reducing the Cost of Group Communication with Semantic View Synchrony
View Synchrony (VS) is a powerful abstraction in the design and implementation of dependable distributed systems. By ensuring that processes deliver the same set of messages in ea...
José Orlando Pereira, Luís Rodrigues...
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
15 years 4 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
CLUSTER
2007
IEEE
15 years 1 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
IPCCC
2007
IEEE
15 years 4 months ago
Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization
Leakage power is a major concern in current microarchitectures as it is increasing exponentially with decreasing transistor feature sizes. In this paper, we present a technique ca...
Santosh Talli, Ram Srinivasan, Jeanine Cook
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
15 years 10 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...