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» Reducing Power in High-Performance Microprocessors
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DAGSTUHL
2006
14 years 11 months ago
Physical 2D Morphware and Power Reduction Methods for Everyone
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
Jürgen Becker, Michael Hübner, Katarina ...
CSREAESA
2003
14 years 11 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
15 years 6 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
ISCA
2012
IEEE
191views Hardware» more  ISCA 2012»
13 years 4 days ago
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...
Timothy N. Miller, Renji Thomas, Xiang Pan, Radu T...
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
14 years 4 months ago
Should we worry about memory loss?
In recent years the High Performance Computing (HPC) industry has benefited from the development of higher density multi-core processors. With recent chips capable of executing u...
O. Perks, Simon D. Hammond, S. J. Pennycook, Steph...