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» Reducing Power in High-Performance Microprocessors
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ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
15 years 4 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
DAC
2001
ACM
15 years 10 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
HPCA
2005
IEEE
15 years 10 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
MASCOTS
2008
14 years 11 months ago
Sensitivity Based Power Management of Enterprise Storage Systems
Energy-efficiency is a key requirement in data centers today. Storage systems constitute a significant fraction of the energy consumed in a data center and therefore enterprise st...
Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan