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» Reducing Power in High-Performance Microprocessors
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DAC
1994
ACM
15 years 1 months ago
A Modular Partitioning Approach for Asynchronous Circuit Synthesis
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
Ruchir Puri, Jun Gu
ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
15 years 4 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
80
Voted
CF
2006
ACM
15 years 1 months ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
DAC
2007
ACM
15 years 10 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
MICRO
2010
IEEE
132views Hardware» more  MICRO 2010»
14 years 7 months ago
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very ...
Timothy N. Miller, Renji Thomas, James Dinan, Bruc...