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» Reducing Power in High-Performance Microprocessors
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TDSC
2010
111views more  TDSC 2010»
14 years 8 months ago
Using Underutilized CPU Resources to Enhance Its Reliability
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Sur...
PPOPP
2006
ACM
15 years 3 months ago
Programming for parallelism and locality with hierarchically tiled arrays
Tiling has proven to be an effective mechanism to develop high performance implementations of algorithms. Tiling can be used to organize computations so that communication costs i...
Ganesh Bikshandi, Jia Guo, Daniel Hoeflinger, Gheo...
79
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ICS
2005
Tsinghua U.
15 years 3 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
MICCAI
2002
Springer
15 years 10 months ago
Robust Registration of Multi-modal Images: Towards Real-Time Clinical Applications
Abstract. High performance computing has become a key step to introduce computer tools, like real-time registration, in the medical field. To achieve real-time processing, one usua...
Radu Stefanescu, Sébastien Ourselin, Xavier...
ICDCN
2010
Springer
15 years 4 months ago
An Intelligent IT Infrastructure for the Future
The proliferation of new modes of communication and collaboration has resulted in an explosion of digital information. To turn this challenge into an opportunity, the IT industry ...
Prith Banerjee