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» Reducing Synchronization Overhead in Parallel Simulation
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ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
15 years 1 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
61
Voted
SPAA
2009
ACM
15 years 10 months ago
Scalable reader-writer locks
We present three new reader-writer lock algorithms that scale under high read-only contention. Many previous reader-writer locks suffer significant degradation when many readers a...
Yossi Lev, Victor Luchangco, Marek Olszewski
NCA
2007
IEEE
15 years 3 months ago
Improving Network Processing Concurrency using TCPServers
Exponentially growing bandwidth requirements and slowing gains in processor speeds have led to the popularity of multiprocessor architectures. Network stack parallelism is increas...
Aniruddha Bohra, Liviu Iftode
79
Voted
IPPS
1999
IEEE
15 years 1 months ago
Using Channels for Multimedia Communication
In this paper we present a paradigm to express streams and its implementation. Streams are a convenient mechanism to communicate multimedia data, for example video or audio, betwe...
David May, Henk L. Muller
ISCA
2012
IEEE
270views Hardware» more  ISCA 2012»
13 years 1 days ago
Revisiting hardware-assisted page walks for virtualized systems
Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current twodimensional (2...
Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh