88 search results - page 6 / 18 » Reducing energy and delay using efficient victim caches |
AINA
2008
IEEE
14 years 11 months ago
2008
IEEE
It is important to design an energy efficient data gathering tree structure for wireless sensor networks. As for the energy efficiency, network's overall energy consumption an...
MICRO
2002
IEEE
14 years 9 months ago
2002
IEEE
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
PDP
2010
IEEE
15 years 1 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...