6568 search results - page 107 / 1314 » Reducing the Complexity of Reductions |
174
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DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
16 years 8 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
199
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ICCD
2004
IEEE
16 years 4 months ago
2004
IEEE
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
231
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APCSAC
2006
IEEE
16 years 1 months ago
2006
IEEE
Abstract. Scheduling algorithms significantly affect the performance of a realtime system. In systems with power constraints, context switches in a schedule result in wasted power ...
177
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ISQED
2006
IEEE
16 years 1 months ago
2006
IEEE
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
192
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DLOG
2006
15 years 9 months ago
2006
We propose a technique to make consistency detection scalable for large Aboxes in secondary storage. We use static analysis of knowledge representation with summarization techniqu...