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» Reducing the Complexity of Reductions
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FMSD
2006
59views more  FMSD 2006»
15 years 6 months ago
Optimistic synchronization-based state-space reduction
Reductions that aggregate fine-grained transitions into coarser transitions can significantly reduce the cost of automated verification, by reducing the size of the state space. W...
Scott D. Stoller, Ernie Cohen
CIKM
2008
Springer
15 years 8 months ago
REDUS: finding reducible subspaces in high dimensional data
Finding latent patterns in high dimensional data is an important research problem with numerous applications. The most well known approaches for high dimensional data analysis are...
Xiang Zhang, Feng Pan, Wei Wang 0010
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
15 years 10 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
ET
2002
64views more  ET 2002»
15 years 6 months ago
Structural Fault Based Specification Reduction for Testing Analog Circuits
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
Seongmoon Wang, Wenlong Wei