221 search results - page 13 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
ASPDAC
2009
ACM
14 years 9 months ago
2009
ACM
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
116
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EMSOFT
2005
Springer
15 years 5 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
IWANN
2007
Springer
15 years 6 months ago
2007
Springer
This paper presents a network architecture to interconnect mixed-signal VLSI1 integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. ...
123
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DSN
2011
IEEE
13 years 11 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
119
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INTEGRATION
2008
14 years 11 months ago
2008
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...